A continuing goal of the semiconductor industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND Flash memory devices). One way of increasing memory density in non-volatile memory devices is to utilize vertical memory array (also referred to as a “three-dimensional (3D) memory array”) architectures. A typical vertical memory array includes semiconductor pillars extending through openings in tiers of conductive structures (e.g., word line plates, control gate plates) and dielectric materials at each junction of the semiconductor pillars and the conductive structures. Such a configuration permits a greater number of switching devices (e.g., transistors) to be located in a unit of die area by building the array upwards (e.g., longitudinally, vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of transistors.
Conventional vertical memory arrays include electrical connections between the conductive structures and access lines (e.g., word lines) so that memory cells in the vertical memory array can be uniquely selected for writing, reading, or erasing operations. One method of forming such an electrical connection includes forming a so-called “staircase” or “stair step” structure at edges of the tiers of conductive structures. The staircase structure includes individual “steps” defining contact regions of the conductive structures upon which contact structures can be positioned to provide electrical access to the conductive structures. Unfortunately, conventional staircase structure fabrication techniques can segment one or more conductive structures of a given tier, resulting in discontinuous conductive paths through the tier that can require the use of multiple (e.g., more than one) switching devices to drive voltages completely across the tier and/or in opposing directions across the tier. In addition, as the number of tiers of conductive structures increases the number of interconnections required to drive voltages across the tiers also increases, requiring undesirable increases in the lateral dimensions of the tiers and/or of the steps of the staircase structures associated with the tiers to accommodate the increased number of interconnections and circumvent undesirable capacitive coupling between the interconnections.
There remains a need for new semiconductor device structures, such as memory array blocks for 3D non-volatile memory devices (e.g., 3D NAND Flash memory devices), as well as for associated memory devices and electronic systems including the semiconductor device structures, and simple, cost-efficient methods of forming semiconductor device structures.